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학술지 Multigigabit CMOS Limiting Amplifier and VCSEL Driver Arrays for Parallel Optical Interconnects
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저자
강세경, 이태우, 박효훈
발행일
200608
출처
Microwave and Optical Technology Letters, v.48 no.8, pp.1656-1659
ISSN
0895-2477
출판사
John Wiley & Sons
DOI
https://dx.doi.org/10.1002/mop.21691
협약과제
06MT2700, OTH기반 40G급 다중서비스 전송 기술개발, 고제수
초록
Limiting amplifier and VCSEL driver arrays for parallel optical interconnects operating at 8 Gb/s are presented, which are designed and fabricated in a Si-based 0.18-μm CMOS technology for the single chip integration with low-power consumption. The limiting amplifier array showed a differential gain of 26 dB, a -3-dB bandwidth of 6.8 GHz, and a crosstalk of -32 dB between channels. For the VCSEL driver array, it showed a differential gain of 25 dB, a -3-dB bandwidth of 6.3 GHz, and crosstalk of -26 dB between channels. The power dissipation per channel of the limiting amplifier and the VCSEL driver are 45 and 120 mW, respectively. © 2006 Wiley Periodicals, Inc.
KSP 제안 키워드
3-dB bandwidth, CMOS Technology, Differential gain, Limiting amplifier, Optical Interconnect(OI), Si-based, Single-Chip, VCSEL driver, chip integration, low power consumption, power dissIPation