상세정보
학술대회
A FEC Architecture for UWB System
- 발행일
- 200609
- 출처
- Vehicular Technology Conference (VTC) 2006 (Fall), pp.1477-1481
- 협약과제
- 06MH2600, 초고속 멀티미디어 전송 UWB 솔루션 개발, 최상성
- 초록
- The MB-OFDM UWB for IEEE802.15.3a uses a R=1/3 convolutional code for the error correcting code. Furthermore, it uses a Reed-Solomon code to protect the PLCP header from impairment. In this paper, we show a detailed hardware architecture and implementation results of FEC (forward error correction) for the MB-OFDM UWB. We propose a Viterbi decoder with radix-4 ACS to resolve the timing problem and we show important parameters which are necessary for the hardware design. The estimated hardware size of the Viterbi decoder is 120k gates and the clock frequency is 144MHz. The proposed Reed-Solomon decoder uses a modified euclidean algorithm to solve a key equation. This RS decoder has low latency and small area using simple and regular processing elements for the key equation solve block. The RS decoder is 27k gates and it can operate at a clock frequency of 232MHz, and has the latency of 46 symbol clocks. When RS code is applied to the whole data field, the area increased to about 3 times. © 2006 IEEE.
- KSP 제안 키워드
- Clock frequency, Data field, Error correcting code(ECC), Forward error correction(FEC), Hardware Architecture, Hardware Design, Key equation, Low latency, MB-OFDM UWB, Modified euclidean algorithm, RS code