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Conference Paper
Fast Settling 9GHz PLL Using 528MHz Reference PLL Clock for MB-OFDM UWB System
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- Authors
- Young Jae Lee, Seok Bong Hyun, Geum Young Tak, Hyun Kyu Yu
- Issue Date
- 2006-09
- Citation
- European Microwave Integrated Circuits Conference (EuMIC) 2006, pp.179-182
- Language
- English
- Type
- Conference Paper
- Abstract
- A CMOS phase-locked loop (PLL) which synthesizes frequencies between 6.336-8.976GHz in steps of 528MHz and settles in approximately 150ns using the 528MHz reference clock is presented. Frequency hopping between the bands in the each mode is critical point to design the PLL in the multi-band orthogonal frequency division multiplexing (OFDM) because the frequency switching between each band is less than 9.5ns. To achieve the fast loop settling, the integer-N PLL that operates with the high reference frequency to meet the settling requirement is implemented. Two PLLs that operate at the 9GHz and 528MHz are integrated and shows the band hopping lower than Ins. © 2006 EuMA.
- KSP Keywords
- Critical point, Fast Settling, Frequency switching, MB-OFDM UWB, Orthogonal frequency division Multiplexing(OFDM), Reference clock, Reference frequency, UWB system, frequency hopping, integer-n, multi-band