상세정보
학술대회
R22 SDF FFT Implementation with Coefficient Memory Reduction Scheme
- 발행일
- 200609
- 출처
- Vehicular Technology Conference (VTC) 2006 (Fall), pp.1535-1538
- 협약과제
- 06MM1700, 다중모드 기지국 시험, 김진업
- 초록
- Fast Fourier Transform (FFT) is a key building block for Orthogonal Frequency Division Multiplexing (OFDM) systems. Due to the development of wireless portable devices, it is important to minimize the size and power of a FFT processor. One of the methods to satisfy such demands is reducing the size of twiddle coefficient memory. This paper presents an effective coefficient memory reduction scheme for a R22SDF FFT implementation. When applying a conventional method to an N-point R22SDF FFT, the number of twiddle coefficients is 3N/4. However, the proposed scheme requires only (N/8+1) coefficients and its additional hardware architecture is very simple. The effectiveness of the proposed method is verified by implementation results on a FPGA. © 2006 IEEE.
- KSP 제안 키워드
- Building block, Conventional methods, FFT processor, Fast fourier transform (fft), Hardware Architecture, Memory reduction, Orthogonal frequency division Multiplexing(OFDM), Portable device, effective coefficients