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Low Complexity Bit-Parallel Squarer for GF(2n) Defined by Irreducible Trinomials
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- Authors
- Sun Mi Park, Ku Young Chang
- Issue Date
- 2006-09
- Citation
- IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E89-A, no.9, pp.2451-2452
- ISSN
- 1745-1337
- Publisher
- 일본, 전자정보통신학회 (IEICE)
- Language
- English
- Type
- Journal Article
- Abstract
- We present a bit-parallel squarer for GF(2n) defined by an irreducible trinomial xn + xk + 1 using a shifted polynomial basis. The proposed squarer requires T(X) delay and at most ?뙂n/2?뙃 XOR gates, where T(X) is the delay of one XOR gate. As a result, the squarer using the shifted polynomial basis is more efficient than one using the polynomial basis except for k = 1 or n/2. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers.
- KSP Keywords
- Bit-parallel, Information and communication, Shifted polynomial basis(SPB), XOR gate, low-complexity