상세정보
학술지
Low Complexity Bit-Parallel Squarer for GF(2n) Defined by Irreducible Trinomials
- 저자
- 박선미, 장구영
- 발행일
- 200609
- 출처
- IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E89-A no.9, pp.2451-2452
- ISSN
- 1745-1337
- 출판사
- 일본, 전자정보통신학회 (IEICE)
- 협약과제
- 06MK2700, 차세대 시큐리티 기술 개발, 조현숙
- 초록
- We present a bit-parallel squarer for GF(2n) defined by an irreducible trinomial xn + xk + 1 using a shifted polynomial basis. The proposed squarer requires T(X) delay and at most ?뙂n/2?뙃 XOR gates, where T(X) is the delay of one XOR gate. As a result, the squarer using the shifted polynomial basis is more efficient than one using the polynomial basis except for k = 1 or n/2. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers.
- KSP 제안 키워드
- Bit-parallel, Information and communication, Shifted polynomial basis(SPB), XOR gate, low-complexity