상세정보
학술대회
A 5-mW 0.26-mm2 10-bit 20-MS/s Pipelined CMOS ADC with Multi-Stage Amplifier Sharing Technique
- 발행일
- 200609
- 출처
- European Solid-State Circuits Conference (ESSCIRC) 2006, pp.544-547
- 협약과제
- 06MB1100, 나노소자기반 회로 설계기술 개발, 김종대
- 초록
- This paper describes a 10-bit 20-MSample/s analog-to-digital converter (ADC) employing a multi-stage amplifier sharing scheme to reduce the power consumption and chip area at low supply voltages. The proposed scheme shares a multi-stage amplifier between a sample-and-hold amplifier and a first-stage multi-bit multiplying digital-to-analog converter by changing loop configurations of the amplifier. For further power and chip area reduction, the same resistor ladder is shared between the adjacent flash ADC blocks. The prototype ADC fabricated in a 0.13-μm CMOS technology shows a signal-to-noise-and-distortion ratio of 56.0 dB and a spurious-free dynamic range of 68.7 dB with a 2-MHz sinusoidal input at 20 MSample/s. The ADC occupies 0.26 mm 2 and dissipates 5 mW at a 1.2-V supply. © 2006 IEEE.
- KSP 제안 키워드
- Amplifier sharing technique, Analog to digital converter(ADC), Area Reduction, CMOS Technology, Chip area, Distortion ratio, First stage, Multi-stage, Power Consumption, Sample-and-hold amplifier, Signal-to-Noise-and-Distortion