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Conference Paper
Low Power AES Hardware Architecture for Radio Frequency Identification
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- Authors
- Moo Seop Kim, Jae Cheol Ryou, Yong Je Choi, Sung Ik Jun
- Issue Date
- 2006-10
- Citation
- International Workshop on Security (IWSEC) 2006 (LNCS 4266), v.4266, pp.353-363
- Language
- English
- Type
- Conference Paper
- Abstract
- We present a new architecture of Advanced Encryption Standard (AES) cryptographic hardware which can be used as cryptographic primitives supporting privacy and authentication for Radio Frequency Identification (RFID). RFID is a technology to identify goods or person containing the tags. While it is a convenient way to track items, it also provides chances to track people and their activities through their belongings. For these reasons, privacy and authentication are a major concern with RFID system and many solutions have been proposed. M. Feldhofer , S. Dominikus, and J. Wolkerstorfer introduced the Interleaved Protocol which serves as a means of authenticating RFID tag to reader devices in [14]. They designed very small and low power AES hardware as a cryptographic primitive. In this contribution, we introduce a novel method to increase the operating speed of previous method for low power AES cryptographic circuits. Our low power AES cryptographic hardware can encrypt 128-bit data block within 870 clock cycles using less than 4000 gates and has a power consumption about or less than 20 μW on a 0.25 μm CMOS process. © Springer-Verlag Berlin Heidelberg 2006.
- KSP Keywords
- Advanced encryption standard, CMOS Process, Cryptographic hardware, Cryptographic primitives, Hardware Architecture, Low-Power, Operating speed, Passive radio frequency identification(RFID), Power Consumption, RFID Tag, RFID system