상세정보
학술대회
A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems
- 발행일
- 200612
- 출처
- Asia Pacific Conference on Circuits and Systems (APCCAS) 2006, pp.339-342
- 협약과제
- 06MB1800, 초저전력 RF/HW/SW 통합 SoC, 현석봉
- 초록
- This work proposes a dual-channel 6b lGS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference preamplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble code correction circuits to optimize power, chip area, and accuracy at lGS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and- distortion ratio of 30dB and a spurious-free dynamic range of 39dB at lGS/s. The measured differential and integral nonlinearities of the prototype ADC are within 1.00LSB and 1.25LSB, respectively. The dual-channel ADC has an active area of 4.0mm2 and consumes 594mW at lGS/s and 1.8V. ©2006 IEEE.
- KSP 제안 키워드
- 0.18um CMOS, Active area, CMOS Technology, Chip area, Communication system, Distortion ratio, Kickback Noise, On-chip, Signal-to-Noise, Track-and-hold, Ultra-Wide Band(UWB)