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Journal Article Low-Voltage and High-Gain Pentacene Inverters with Plasma-Enhanced Atomic-Layer-Deposited Gate Dielectrics
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Authors
Jae Bon Koo, Sun Jin Yun, Jung Wook Lim, Seong Hyun Kim, Chan Hoe Ku, Sang Chul Lim, Jung Hun Lee, Tae Hyoung Zyung
Issue Date
2006-12
Citation
Applied Physics Letters, v.89, no.3, pp.1-3
ISSN
0003-6951
Publisher
American Institute of Physics (AIP)
Language
English
Type
Journal Article
DOI
https://dx.doi.org/10.1063/1.2234835
Abstract
The pentacene thin-film transistors with the plasma-enhanced atomic-layer-deposited 150 nm thick A12O3 or 120 nm thick ZrO2 have been operated at gate voltages between -3 and 3 V. The inverter with a ZrO2 gate dielectric shows a gain of 49 and a full swing from supply voltage (Vdd) to 0 V, operating at input voltages (Vin) from 0 to -1 V and at Vdd of -1 V. The hysteresis observed in the voltage transfer characteristic of the inverter depends on the scan range of Vin applied to the driver transistor, regardless of the Vdd applied to the load transistor. © 2006 American Institute of Physics.
KSP Keywords
20 nm, 3 V, Full Swing, Pentacene thin-film transistors, Plasma-enhanced, Supply voltage, Thin-Film Transistor(TFT), gate dielectric, high gain, low voltage, scan range