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Conference Paper
A 1.25Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with an Improved Effective Phase Resolution
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- Authors
- Chang Kyung Seong, Seung Woo Lee, Woo Young Choi
- Issue Date
- 2005-10
- Citation
- International SoC Design Conference (ISOCC) 2005, pp.247-250
- Language
- English
- Type
- Conference Paper
- Abstract
- A novel 1.25Gb/s digitally-controlled dualloop clock and data recovery circuit (CDR) for multichannel application is proposed. The CDR has a new configuration to improve the phase resolution. A prototype CDR was designed and fabricated in 0.18 ㎛ CMOS technology and its functions were verified with HSPICE simulation and chip measurement.
- KSP Keywords
- CMOS Technology, Clock and Data Recovery Circuit(CDR), Digitally controlled, Dual-loop, HSPICE simulation, Multichannel application, Phase resolution