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Conference Paper
A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS
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- Issue Date
- 2007-02
- Citation
- International Solid-State Circuits Conference (ISSCC) 2007, pp.456-615
- Language
- English
- Type
- Conference Paper
- Abstract
- A 4.7mW 10b 30MS/S pipelined ADC is implemented without a front-end S/H for low power consumption and small area. The prototype ADC, fabricated in a 90nm CMOS process, shows an SNDR of 58.4dB and an SFDR of 75.2dB with a 2MHz sinusoidal input sampled at 30MS/S. The 0.32mm2 chip dissipates 4.7mW at a 1V supply and has a FOM of 0.23pJ/conversion-step. © 2007 IEEE.
- KSP Keywords
- CMOS Process, Front-End, Pipelined ADC, Small area, low power consumption