상세정보
학술대회
A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS
- 발행일
- 200702
- 출처
- International Solid-State Circuits Conference (ISSCC) 2007, pp.456-615
- 협약과제
- 06MB1100, 나노소자기반 회로 설계기술 개발, 김종대
- 초록
- A 4.7mW 10b 30MS/S pipelined ADC is implemented without a front-end S/H for low power consumption and small area. The prototype ADC, fabricated in a 90nm CMOS process, shows an SNDR of 58.4dB and an SFDR of 75.2dB with a 2MHz sinusoidal input sampled at 30MS/S. The 0.32mm2 chip dissipates 4.7mW at a 1V supply and has a FOM of 0.23pJ/conversion-step. © 2007 IEEE.
- KSP 제안 키워드
- CMOS Process, Front-End, Pipelined ADC, Small area, low power consumption