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Conference Paper
A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications
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- Authors
- Seung-Chul Lee, Young-Deuk Jeon, Kwi-Dong Kim, Jong-Kee Kwon, Jong Dae Kim, Jeong-Woong Moon, Woo Yol Lee
- Issue Date
- 2007-02
- Citation
- International Solid-State Circuits Conference (ISSCC) 2007, pp.458-615
- Language
- English
- Type
- Conference Paper
- Abstract
- A 10b 205MS/s 1mm2 ADC for flat-panel display applications is implemented in a 90nm CMOS process. The ADC with an LDO regulator achieves a 53dB PSRR for a 100MHz noise tone and a 55.2dB SNDR for a 30MHz 1Vpp single-ended input at 205MS/s. The core ADC power consumption is 40mW from a 1V non-regulated supply. © 2007 IEEE.
- KSP Keywords
- CMOS Process, Display applications, LDO Regulator, Pipeline ADC, Power Consumption, Single-Ended, flat panel display(FPD)