상세정보
학술대회
A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications
- 발행일
- 200702
- 출처
- International Solid-State Circuits Conference (ISSCC) 2007, pp.458-615
- 협약과제
- 06MB1100, 나노소자기반 회로 설계기술 개발, 김종대
- 초록
- A 10b 205MS/s 1mm2 ADC for flat-panel display applications is implemented in a 90nm CMOS process. The ADC with an LDO regulator achieves a 53dB PSRR for a 100MHz noise tone and a 55.2dB SNDR for a 30MHz 1Vpp single-ended input at 205MS/s. The core ADC power consumption is 40mW from a 1V non-regulated supply. © 2007 IEEE.
- KSP 제안 키워드
- CMOS Process, Display applications, LDO Regulator, Pipeline ADC, Power Consumption, Single-Ended, flat panel display(FPD)