상세정보
학술대회
Arbitrary Bit Generation and Correction Technique for Encoding QC-LDPC Codes with Dual-Diagonal Parity Structure
- 발행일
- 200703
- 출처
- Wireless Communications and Networking Conference (WCNC) 2007, pp.663-667
- 협약과제
- 07MM1500, 3Gbps급 4G 무선 LAN 시스템 개발, 방승찬
- 초록
- In this paper, we propose a simple yet low complex systematic LDPC encoding method for class of quasi-cyclic low-density parity-check (QC-LDPC) codes which have an efficient encoding / decoding algorithm due to the simple structure of their parity-check matrices. The proposed encoding method is applicable to parity-check matrices having dual-diagonal parity structure with single column of weight 3. Unlike finding a direct solution for parity bits in schemes [5][6], the proposed scheme first generates arbitrary parity bits. Then, given the parity bits for the first sub-block and exploiting the dual-diagonal structure, all parity bits are found through correction. With slight modification of parity-check matrix H, proposed LDPC encoding scheme is directly applicable to matrices defined in IEEE physical layer standards [1][2] with almost negligible performance loss. Moreover, the overall computational complexity involving encoding process is lower than well-known Richardson's efficient encoding scheme [5]. © 2007 IEEE.
- KSP 제안 키워드
- Computational complexity, Direct solution, Encoding method, LDPC encoding, Low Density Parity Check(LDPC), Performance loss, Physical Layer, QC-LDPC codes, Quasi-Cyclic(QC), Quasi-cyclic low-density parity-check(QC-LDPC), Single column