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학술대회 A Hardware Efficient LDPC Encoding Scheme for Exploiting Decoder Structure and Resources
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저자
윤찬호, 오종의, 정민호, 이석규
발행일
200704
출처
Vehicular Technology Conference (VTC) 2007 (Spring), pp.2445-2449
DOI
https://dx.doi.org/10.1109/VETECS.2007.504
협약과제
07MM1500, 3Gbps급 4G 무선 LAN 시스템 개발, 방승찬
초록
Previously, there has been no report on implementation effort to integrate LDPC encoder and decoder into a single hardware. In this paper, we propose a simple yet low complex systematic LDPC encoding method for class of quasicyclic low-density parity-check (QC-LDPC) codes to let LDPC encoder acquire an interchangeable structure, exploited in the decoder. With the proposed encoding scheme, implementation of the proposed encoder becomes much more hardware efficient than having a separate hardware due to LDPC encoder and decoder resource sharing. Moreover, the overall computational complexity of the proposed encoding scheme is lower than the well-known Richardson's efficient encoding scheme [5]. © 2007 IEEE.
KSP 제안 키워드
Computational complexity, Encoder and Decoder, Encoding method, Hardware efficient, LDPC Encoder, LDPC encoding, Low Density Parity Check(LDPC), Quasi-cyclic low-density parity-check(QC-LDPC), encoding scheme, resource sharing