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Journal Article A 9-Bit 80-MS/s CMOS Pipelined Folding A/D Converter with an Offset Canceling Technique
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Authors
Seung-Chul Lee, Young-Deuk Jeon, Jong-Kee Kwon
Issue Date
2007-06
Citation
ETRI Journal, v.29, no.3, pp.408-410
ISSN
1225-6463
Publisher
한국전자통신연구원 (ETRI)
Language
English
Type
Journal Article
DOI
https://dx.doi.org/10.4218/etrij.07.0206.0180
Abstract
A 9-bit 80-MS/s CMOS pipelined folding analog-to-digital converter employing offset-canceled preamplifiers and a subranging scheme is proposed to extend the resolution of a folding architecture. A fully differential dedecoupled structure achieves high linearity in circuit design. The measured differential nonlinearity and integral nonlinearity of the prototype are 짹0.6 LSB and 짹1.6 LSB, respectively.
KSP Keywords
A/D converter, Analog to digital converter(ADC), Fully differential, circuit design, differential nonlinearity(DNL), high linearity, integral nonlinearity