상세정보
학술대회
A 1.8 V-to-2.5 V MIPI RFFE Slave Interface CMOS Circuit
- 발행일
- 201507
- 출처
- International Conference on Advanced Communication Technology (ICACT) 2015, pp.560-563
- 협약과제
- 14PI2100, LTE-A기지국용 전력증폭기를 포함하는 RF Transceiver통합칩 개발, 박봉혁
- 초록
- The MIPI RFFE slave interface circuit including Power-on-Reset (PoR), SCLK receiver and SDATA bidirectional transceiver has been implemented with a CMOS 250 nm process. Simulation results show that the designed circuit has SDATA output transition time (for rise and fall) of shorter than 3.3 ns at a full-speed rate of 26 MHz, which satisfies the timing requirement (< 6.5 ns) by the specification of MD?I RFFE version 1.10. The target load capacitance that the designed MIPI RFFE slave interface circuit drives is 26 pF for the configuration of one master and eight slaves.
- KSP 제안 키워드
- 6 MHz, CMOS circuits, Interface circuit, Load capacitance, Power-On-Reset, simulation results, transition time, version 1