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Conference Paper A 1.8 V-to-2.5 V MIPI RFFE Slave Interface CMOS Circuit
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Authors
Seunghyun Jang, Namsik Ryu, Hui Dong Lee, Bonghyuk Park
Issue Date
2015-07
Citation
International Conference on Advanced Communication Technology (ICACT) 2015, pp.560-563
Language
English
Type
Conference Paper
DOI
https://dx.doi.org/10.1109/ICACT.2015.7224858
Project Code
14PI2100, Development of RF Transceiver including PA for LTE-A Base-station, Park Bong Hyuk
Abstract
The MIPI RFFE slave interface circuit including Power-on-Reset (PoR), SCLK receiver and SDATA bidirectional transceiver has been implemented with a CMOS 250 nm process. Simulation results show that the designed circuit has SDATA output transition time (for rise and fall) of shorter than 3.3 ns at a full-speed rate of 26 MHz, which satisfies the timing requirement (< 6.5 ns) by the specification of MD?I RFFE version 1.10. The target load capacitance that the designed MIPI RFFE slave interface circuit drives is 26 pF for the configuration of one master and eight slaves.
KSP Keywords
6 MHz, CMOS circuits, Interface circuit, Load capacitance, Power-On-Reset, simulation results, transition time, version 1