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Journal Article A CMOS Frequency Synthesizer Block for MB-OFDM UWB Systems
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Authors
Chang-Wan Kim, Sang-Sung Choi, Sang-Gug Lee
Issue Date
2007-08
Citation
ETRI Journal, v.29, no.4, pp.437-444
ISSN
1225-6463
Publisher
한국전자통신연구원 (ETRI)
Language
English
Type
Journal Article
DOI
https://dx.doi.org/10.4218/etrij.07.0106.0207
Abstract
A CMOS frequency synthesizer block for multi-band orthogonal frequency division multiplexing ultrawideband systems is proposed. The proposed frequency synthesizer adopts a double-conversion architecture for simplicity and to mitigate spur suppression requirements for out-of-band interferers in 2.4 and 5 GHz bands. Moreover, the frequency synthesizer can consist of the fewest nonlinear components, such as divide-by-Ns and a mixer with the proposed frequency plan, leading to the generation of less spurs. To evaluate the feasibility of the proposed idea, the frequency synthesizer block is implemented in 0.18-μm CMOS technology. The measured sideband suppression ratio is about 32 dBc, and the phase noise is -105 dBc/Hz at an offset of 1 MHz. The fabricated chip consumes 17.6 mA from a 1.8 V supply, and the die-area including pads is 0.9 × 1.1 mm2.