상세정보
학술지
A 3.1 to 5 GHz CMOS Transceiver for DS-UWB Systems
- 발행일
- 200708
- 출처
- ETRI Journal, v.29 no.4, pp.421-429
- ISSN
- 1225-6463
- 출판사
- 한국전자통신연구원 (ETRI)
- 협약과제
- 06MH2600, 초고속 멀티미디어 전송 UWB 솔루션 개발, 최상성
- 초록
- This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 mm2 die using standard 0.18 μm CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.
- KSP 제안 키워드
- 5 GHz, Building block, CMOS Technology, CMOS Transceiver, Current consumption, DS-UWB, Direct Conversion, Down-conversion mixer, Driver Amplifier, Gain flatness, I/Q demodulator