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Conference Paper
A New Burst Mode Clock and Data Recovery Circuit
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- Authors
- Seung-Woo Lee, Chang-Kyung Seong, Bhum-Cheol Lee, Woo-Young Choi
- Issue Date
- 2007-10
- Citation
- International SoC Design Conference (ISOCC) 2007, pp.215-218
- Language
- English
- Type
- Conference Paper
- Abstract
- A new burst mode digital clock and data recovery circuit having characteristics of fast acquisition time and jitter reduction is proposed for PON and switch applications. Its simple structure is composed of digital phase aligner, phase interpolator and meta-stability resistant digital logics. The proposed circuit has low latency and data recovery after two data bits. Simulation results show that the proposed circuit reduces rms jitter by 30% and operates no errors at 2 7 -1 PRBS with 200ppm frequency offset. Its power dissipation is 7.6mW at 1.8V and layout occupation area is 100 x 110µm2.