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Thermal Annealing Effects on the Electrical Characteristics of the Back Interface in Nano-silicon-on-insulator Channel
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- Authors
- Won-Ju Cho, Chang-Geun Ahn
- Issue Date
- 2007-04
- Citation
- Applied Physics Letters, v.90, no.14, pp.1-3
- ISSN
- 0003-6951
- Publisher
- American Institute of Physics (AIP)
- Language
- English
- Type
- Journal Article
- Abstract
- The electrical properties of the back interface between the thin silicon and buried-oxide layers of nano-silicon-on-insulator substrate were evaluated. The effects of rapid thermal annealing (RTA) process were investigated, and the distributions of interface states at the thin silicon/buried-oxide interface were estimated by using metal-point-contact field-effect-transistor method. The interface-states at the back interface were considerably increased by RTA process. The RTA higher than 800 °C contributes to the increase of acceptor-type interface states. The increased interface states were effectively reduced by conventional furnace annealing at 500 °C in nitrogen ambient. © 2007 American Institute of Physics.
- KSP Keywords
- Annealing effects, Back interface, Conventional furnace annealing, Electrical characteristics, Electrical properties, Field Effect Transistor(FET), RTA process, Rapid thermal annealing(RTA), Silicon On Insulator(SOI), Thin silicon, interface states