상세정보
학술지
Thermal Annealing Effects on the Electrical Characteristics of the Back Interface in Nano-silicon-on-insulator Channel
- 저자
- 조원주, 안창근
- 발행일
- 200704
- 출처
- Applied Physics Letters, v.90 no.14, pp.1-3
- ISSN
- 0003-6951
- 출판사
- American Institute of Physics (AIP)
- 협약과제
- 07MB2700, 유비쿼터스 건강관리용 모듈 시스템, 박선희
- 초록
- The electrical properties of the back interface between the thin silicon and buried-oxide layers of nano-silicon-on-insulator substrate were evaluated. The effects of rapid thermal annealing (RTA) process were investigated, and the distributions of interface states at the thin silicon/buried-oxide interface were estimated by using metal-point-contact field-effect-transistor method. The interface-states at the back interface were considerably increased by RTA process. The RTA higher than 800 °C contributes to the increase of acceptor-type interface states. The increased interface states were effectively reduced by conventional furnace annealing at 500 °C in nitrogen ambient. © 2007 American Institute of Physics.
- KSP 제안 키워드
- Annealing effects, Back interface, Conventional furnace annealing, Field-effect transistors(FETs), Interface states, Nano-silicon, Oxide interface, Oxide layer, RTA process, Silicon On Insulator(SOI), Thin silicon