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Conference Paper
Power Efficient Hardware Architecture of SHA-1 Algorithm for Trusted Mobile Computing
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- Authors
- Moo Seop Kim, Jae Cheol Ryou
- Issue Date
- 2007-12
- Citation
- International Conference on Information and Communications Security (ICICS) 2007 (LNCS 4861), v.4861, pp.375-385
- Language
- English
- Type
- Conference Paper
- Project Code
- 07MK1500, Development of a common security core module for supporting secure and trusted service in the next generation mobile terminals, Jun Sungik
- Abstract
- The Trusted Mobile Platform (TMP) is developed and promoted by the Trusted Computing Group (TCG), which is an industry standard body to enhance the security of the mobile computing environment. The built-in SHA-1 engine in TMP is one of the most important circuit blocks and contributes the performance of the whole platform because it is used as key primitives supporting platform integrity and command authentication. Mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for low power SHA-1 circuit are required. In this paper, we present a novel and efficient hardware architecture of low power SHA-1 design for TMP. Our low power SHA-1 hardware can compute 512-bit data block using less than 7,000 gates and has a power consumption about 1.1 m A on a 0.25μm CMOS process. © Springer-Verlag Berlin Heidelberg 2007.
- KSP Keywords
- Built-in, CMOS Process, Command authentication, Computing environment, Design method, Efficient Hardware Architecture, Industry standard, Low-Power, Mobile computing, Mobile platform, Power Consumption