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학술지 A 20 Gb/s 1:4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 μm CMOS Technology
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저자
김병국, 김이섭, 변상진, 유현규
발행일
200802
출처
IEEE Journal of Solid-State Circuits, v.43 no.2, pp.541-549
ISSN
0018-9200
출판사
IEEE
DOI
https://dx.doi.org/10.1109/JSSC.2007.914332
협약과제
07MB2300, 오디오 비디오 신호처리용 임베디드 DSP Platform, 엄낙웅
초록
In this paper, a 20 Gb/s 1:4 DEMUX without inductors is presented. A coupled latch with shared current source and buffer insertion scheme improves the signal bandwidth. A divide-by-2 circuit with a static frequency divider and a delay-locked loop achieves low power consumption and enhanced timing margin without the degradation of the divider sensitivity. A horizontal eye opening is 71.3%, and a vertical eye opening is 52%. The test chip fabricated in a 0.13 μm process consumes 210 mW from 1.2 V logic supply. © 2008 IEEE.
KSP 제안 키워드
CMOS Technology, Current source, Delay-Locked Loop, Test Chip, buffer insertion, divide-by-2, eye opening, low power consumption, signal bandwidth, static frequency divider, timing margin