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A 20 Gb/s 1:4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 μm CMOS Technology
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- Authors
- Byung-Guk Kim, Lee-Sup Kim, Sang Jin Byun, Hyun-Kyu Yu
- Issue Date
- 2008-02
- Citation
- IEEE Journal of Solid-State Circuits, v.43, no.2, pp.541-549
- ISSN
- 0018-9200
- Publisher
- IEEE
- Language
- English
- Type
- Journal Article
- Abstract
- In this paper, a 20 Gb/s 1:4 DEMUX without inductors is presented. A coupled latch with shared current source and buffer insertion scheme improves the signal bandwidth. A divide-by-2 circuit with a static frequency divider and a delay-locked loop achieves low power consumption and enhanced timing margin without the degradation of the divider sensitivity. A horizontal eye opening is 71.3%, and a vertical eye opening is 52%. The test chip fabricated in a 0.13 μm process consumes 210 mW from 1.2 V logic supply. © 2008 IEEE.
- KSP Keywords
- CMOS Technology, Current source, Delay-Locked Loop, Low Power consumption, Test Chip, buffer insertion, divide-by-2, eye opening, signal bandwidth, static frequency divider, timing margin