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학술지 Er and Pt Gate Electrodes Formed on SiO2 Gate Dielectrics
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저자
최철종, 정원진, 김약연, 전명심, 김태엽, 장문규, 송명호, 이성재
발행일
200711
출처
Electrochemical and Solid-State Letters, v.11 no.2, pp.H22-H25
ISSN
1099-0062
출판사
Electrochemical Society (ECS)
DOI
https://dx.doi.org/10.1149/1.2812433
협약과제
08ZB1400, 유비쿼터스 라이프케어 원천요소기술 개발, 박선희
초록
We investigated the electrical and structural properties of WEr SiO2 and Pt SiO2 gate stacks. WEr SiO2 gate stacks exhibited increased capacitance after rapid thermal annealing (RTA) process while the capacitance of Pt SiO2 gate stacks remained unchangeable regardless of RTA process. Because of the physical plasma damage that occurred during the sputtering deposition process, Pt penetration led to a decrease in the SiO2 film thickness of Pt SiO2 gate stacks. This resulted in the reduction of the equivalent oxide thickness compared to the poly-Si SiO2 gate stack. A relatively small flatband voltage shift of WEr SiO2 gate stacks was attributed to the reduction of effective oxide charge caused by interfacial reaction between Er and SiO2 films. © 2007 The Electrochemical Society.
KSP 제안 키워드
Electrical and structural properties, Flatband voltage shift, Gate stack, Interfacial reaction, Polycrystalline silicon(poly-Si), RTA process, Sputtering deposition, deposition process, equivalent oxide thickness, film thickness, gate dielectric