상세정보
학술지
Three-Dimensionally Stacked Poly-Si TFT CMOS Inverter with High Quality Laser Crystallized Channel on Si Substrate
- 발행일
- 200803
- 출처
- Solid-State Electronics, v.52 no.3, pp.372-376
- ISSN
- 0038-1101
- 출판사
- Elsevier
- 협약과제
- 07ZB1200, 정보통신미래신기술연구사업, 정태형
- 초록
- 3D stacked poly-Si CMOS inverters with a high quality laser crystallized channel were fabricated on bulk Si wafers. In order to fabricate 3D stacked poly-Si CMOS inverters, the PMOS thin-film-transistor (TFT) at upper poly-Si layer were stacked on the NMOS TFT at lower poly-Si layer and interlayer dielectric film. After laser crystallization, grains in poly-Si films were very uniform and the dominant crystalline orientation was (1 1 1) direction. The sub-threshold swing of NMOS and PMOS TFTs was very good, showing 78 mV/dec. and 86 mV/dec., respectively. And the maximum/minimum current ratio of both TFTs was larger than 107 which is equivalent to those at the bulk or SOI MOSFET. The DC voltage transfer characteristics and transient characteristics of stacked poly-Si CMOS inverter were good enough for the vertical integrated CMOS applications. We verified the feasibility of 3D stacked CMOS inverter circuit by poly-Si TFT technology. © 2007 Elsevier Ltd. All rights reserved.
- KSP 제안 키워드
- 3D stacked, CMOS applications, CMOS inverter circuit, Crystalline orientation, Current ratio, DC voltage, Dielectric films, Interlayer dielectric, Laser crystallization, Laser crystallized channel, Minimum current