상세정보
학술지
A 40 Gb/s Clock and Data Recovery Module with Improved Phase-Locked Loop Circuits
- 발행일
- 200804
- 출처
- ETRI Journal, v.30 no.2, pp.275-281
- ISSN
- 1225-6463
- 출판사
- 한국전자통신연구원 (ETRI)
- 협약과제
- 07MT2400, OTH기반 40G급 다중서비스 전송 기술개발, 고제수
- 초록
- A 40 Gb/s clock and data recovery (CDR) module for a fiber-optic receiver with improved phase-locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D-type flip-flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo-random binary sequence (231-1) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D-FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.
- KSP 제안 키워드
- 40 gb/s, Clock and Data Recovery, Clock recovery(CR), Decision circuit, Fiber optic, Flip-flop, Pseudo Random Binary Sequence(PRBS), Recovery module, clock signal, frequency acquisition, phase-locked loop(PLL)