상세정보
학술대회
A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC Decoder
- 발행일
- 200805
- 출처
- International Symposium on Circuits and Systems (ISCAS) 2008, pp.3462-3465
- 협약과제
- 07MB3700, MPCore 플랫폼 기반 다중 포맷 멀티미디어 SoC, 엄낙웅
- 초록
- In this paper, we implement the configurable processor for CAVLC function module of a H.264/AVC Baseline profile decoder as the starting point to implement the H.264/AVC decoder system in a multi processor platform. The requirements of the implementations are the low-power processor and speed optimized algorithms tailored to the processor architecture. An arithmetic formula mapping method for fast CAVLC algorithms and a dual-issue VLIW processor architecture with custom instructions are proposed. The experiment results show that the synthesized processor has about 75K gates and can carry out the decoding of 30-fps CIF (352x288 pixels) images around 120 Mega cycles. ©2008 IEEE.
- KSP 제안 키워드
- Application-specific, Carry out, Configurable processor, Custom instructions, Experiment results, Function modules, Low-Power, Mapping method, Optimized algorithm, Power processor, Processor architecture