BROWSE
Detail
Conference Paper
A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC Decoder
Cited 3 time in 
Share 
Share
- Issue Date
- 2008-05
- Citation
- International Symposium on Circuits and Systems (ISCAS) 2008, pp.3462-3465
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- In this paper, we implement the configurable processor for CAVLC function module of a H.264/AVC Baseline profile decoder as the starting point to implement the H.264/AVC decoder system in a multi processor platform. The requirements of the implementations are the low-power processor and speed optimized algorithms tailored to the processor architecture. An arithmetic formula mapping method for fast CAVLC algorithms and a dual-issue VLIW processor architecture with custom instructions are proposed. The experiment results show that the synthesized processor has about 75K gates and can carry out the decoding of 30-fps CIF (352x288 pixels) images around 120 Mega cycles. ©2008 IEEE.
- KSP Keywords
- Carry out, Configurable processor, Custom instructions, Experiment results, Function module, Low-Power, Mapping method, Optimized algorithm, Power processor, Processor architecture, Starting point