본 논문에서는 URP(Universal Reconfigurable Processor)에서의 전역 탐색 움직임 예측 알고리듬을 제안한다. URP는 partitioned SIMD 동작이 가능하고, 4x32개의 프로세싱 유닛, 32개의 부동 소수점 누산기, 제어 유닛, 데이터 메모리 등으로 구성되어 있다. 제안되는 알고리듬은 H.264/AVC에서 필요한 7가지 크기의 블록에 대한 움직임 예측을 수행하며, 각 크기의 블록에 대한 최소 SAD(Sum of Absolute Difference), 움직임 벡터, 창조 프레임 인덱스를 계산한다. 제안되는 알고리듬은 URP에서 8개의 현재 블록에 대한 연산을 동시에 처리하며, 100㎒에서 CIF(352x288)급 이미지를 30 frame/s로 처리하는데 약 0.86초가 소요된다.
KSP Keywords
Reconfigurable Processor, Sum of absolute differences(SAD)
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