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Detail
Journal Article
Low Temperature Characteristics of Schottky Barrier Single Electron and Single Hole Transistors
- Authors
- Moongyu Jang, Myungsim Jun, Taehyoung Zyung
- Issue Date
- 2012-12
- Citation
- ETRI Journal, v.34, no.6, pp.950-953
- ISSN
- 1225-6463
- Publisher
- 한국전자통신연구원 (ETRI)
- Language
- English
- Type
- Journal Article
- Abstract
- Schottky barrier single electron transistors (SB-SETs) and Schottky barrier single hole transistors (SB-SHTs) are fabricated on a 20-nm thin silicon-on-insulator substrate incorporating e-beam lithography and a conventional CMOS process technique. Erbium- and platinum-silicide are used as the source and drain material for the SB-SET and SB-SHT, respectively. The manufactured SB-SET and SB-SHT show typical transistor behavior at room temperature with a high drive current of 550 μA/μm and -376 μA/μm, respectively. At 7 K, these devices show SET and SHT characteristics. For the SB-SHT case, the oscillation period is 0.22 V, and the estimated quantum dot size is 16.8 nm. The transconductance is 0.05 μS and 1.2 μS for the SB-SET and SB-SHT, respectively. In the SB-SET and SB-SHT, a high transconductance can be easily achieved as the silicided electrode eliminates a parasitic resistance. Moreover, the SB-SET and SB-SHT can be operated as a conventional field-effect transistor (FET) and SET/SHT depending on the bias conditions, which is very promising for SET/FET hybrid applications. This work is the first report on the successful operations of SET/SHT in Schottky barrier devices. © 2012 ETRI.
- KSP Keywords
- CMOS Process, Drive Current, E-beam Lithography, Field-effect transistors(FETs), Hybrid Application, Low temperature(LT), Low temperature characteristics, Oscillation period, Process technique, Quantum Dot(QD), Room-temperature