상세정보
학술대회
Implemention of 128-Point Fast Fourier Transform Processor for UWB Systems
- 발행일
- 200808
- 출처
- International Wireless Communications and Mobile Computing Conference (IWCMC) 2008, pp.210-213
- 협약과제
- 08MC2200, 초고속 멀티미디어 전송 UWB 솔루션 개발, 최상성
- 초록
- In this paper, we present a 4-parallel fast Fourier transform (FFT) processor for a multi-band orthogonal frequency division multiplexing (MB-OFDM) ultra wideband (UWB) system. The proposed FFT processor utilizes radix-2 4 structure so as to significantly enhance the hardware complexity by reducing the numbers of multipliers and adders. The hardware efficient 4-parellel 128-point FFT processor employing the decimation-in-frequency (DIF) and the singlepath delay feedback (SDF) algorithms can support throughput rates of up to 1 Gsample/s. The proposed FFT processor is implemented and tested by adopting the 0.18 μm CMOS technology with a supply voltage of 1.8 V. © 2008 IEEE.
- KSP 제안 키워드
- CMOS Technology, Decimation-in-frequency, FFT processor, Fast fourier transform (fft), Hardware complexity, Hardware efficient, MB-OFDM, Orthogonal frequency division Multiplexing(OFDM), Supply voltage, UWB system, Ultra-Wide Band(UWB)