07MH1700, Development of UWB Solution for High Speed Multimedia Transmission,
Sangsung Choi
Abstract
This paper presents a parallel processing searcher structure for the initial synchronization of a direct sequence ultra-wideband (DS-UWB) system, which is suitable for the digital implementation of baseband functionalities with a 132 Gsample/s chip rate analog-to-digital converter. An initial timing acquisition algorithm and a data demodulation method are also studied. The proposed searcher effectively acquires initial symbol and frame timing during the preamble transmission period. A hardware efficient receiver structure using 24 parallel digital correlators for binary phase-shift keying DS-UWB transmission is presented. The proposed correlator structure operating at 55 MHz is shared for correlation operations in a searcher, a channel estimator, and the demodulator of a RAKE receiver. We also present a pseudo-random noise sequence generated with a primitive polynomial, 1+x2+x5, for packet detection, automatic gain control, and initial timing acquisition. Simulation results show that the performance of the proposed parallel processing searcher employing the presented pseudo-random noise sequence outperforms that employing a preamble sequence in the IEEE 802.153a DS-UWB proposal.
KSP Keywords
Analog to digital converter(ADC), Automatic Gain Control(AGC), Binary Phase Shift Keying, Channel Estimator, DS-UWB, Demodulation method, Digital correlators, Digital implementation, Direct-sequence(DS), Hardware efficient, IEEE 802.1
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