상세정보
학술대회
A 159.2mW SoC Implementation of T-DMB Receiver including Stacked Memories
- 발행일
- 200809
- 출처
- Custom Integrated Circuits Conference (CICC) 2008, pp.679-682
- 협약과제
- 08MR3700, 지상파 DMB 전송 고도화 기술개발, 임종수
- 초록
- This paper describes a system on chip (SoC) implementation of terrestrial digital multimedia broadcasting (T-DMB) receiver which integrates RF tuner, analog to digital converter (ADC), baseband processor, and multimedia processor in single silicon wafer. The pseudo-SRAM (PSRAM) and SDRAM are doubly stacked with method of silicon in package (SIP). A low-IF RF tuner and a 10bits pipelined ADC is used in this work as TP cores. Baseband processor contains Eureka-147 digital audio broadcasting (DAB) modem, MPEG1-Layer2 decoder, and outer decoder for T-DMB. Multimedia processor is consists of 32bit embedded micro processor, 24bit fixed-point DSP, and H.264/AVC hardware core. The T-DMB SoC was fabricated by using 0.13um 1poly 8metal (1PSM) CMOS process and it gives successful performance of 159.2mW total power dissipation including PSRAM and SDRAM at supply voltages of 1.2V, 2.5V for core and I/O respectively. © 2008 IEEE.
- KSP 제안 키워드
- Analog to digital converter(ADC), Baseband processor, CMOS Process, Digital Audio Broadcasting, Digital multimedia broadcasting, Eureka-147, Fixed-point, Low-IF, Micro-processor, Pipelined ADC, Silicon wafer