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100-Gb/s Three-parallel Reed-Solomon Based Foward Error Correction Architecture for Optical Communications
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- Authors
- Han Ho Lee, Chang-Seok Choi, Jong Yoon Shin, Je-Soo Ko
- Issue Date
- 2008-11
- Citation
- International SoC Design Conference (ISOCC) 2008, pp.I-265-I-268
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper presents a high-speed Forward Error Correction (FEC) architecture based on three-parallel Reed- Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. A high-speed three-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 100-Gb/s RS-FEC architecture. The proposed 100-Gb/s RS-FEC has been implemented with 0.13-μm CMOS standard cell technology in a supply voltage of 1.2V. The implementation results show that 16-Ch. RS-FEC architecture can operate at a clock frequency of 300MHz and has a throughput of 115-Gb/s for 0.13-μm CMOS technology. ©2008 IEEE.
- KSP Keywords
- CMOS Technology, Clock frequency, Forward error correction(FEC), High Speed, Next-generation, Reed Solomon(RS), Standard Cell, Supply voltage, optical communication systems, three-parallel