International Conference on Applied Computer Science (ACS) 2008, pp.1-6
Publisher
WSEAS
Language
English
Type
Conference Paper
Abstract
This paper relates to session management architecture and mechanism for implementing an FPGA-based stateful intrusion detection system. Our proposed architecture can help to perform Stateful Packet Inspection (SPI) in real time using a new session table management scheme that allows more efficient generation of session state information in intrusion detection system. SPI is an important technique to reduce false positive alerts in network intrusion detection system (NIDS). As the number of session increases, this technique requires a higher processing speed, thereby causing performance problems. However, existing software-based solutions cannot perform real-time packet inspection ensuring the wire speed. To guarantee both performance and functionality with respect to statefulness, we designed and implemented SPI-based intrusion detection module in a FPGA to help alleviating a bottleneck in network intrusion detection systems in this paper.
KSP Keywords
False positive, Intrusion Detection Systems(IDSs), Intrusion detection system(IDS), Number of Session, Packet inspection, Processing speed, Real-time packet, Session management, State information, Wire speed, management scheme
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