상세정보
학술대회
Design of High Energy Efficiency 32bit Processing Unit Using Instruction-Levels Data Gating and Dynamic Voltage Scaling techniques
- 발행일
- 200811
- 출처
- International SoC Design Conference (ISOCC) 2008, pp.II-69-II-72
- 협약과제
- 08MB1800, 유비쿼터스 단말용 부품 모듈, 김종대
- 초록
- This paper describes design and circuit simulation of the high energy efficiency 32bit processing unit (PU) using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating and DVS technique. We can control activation and switching activity of the function units using the proposed data gating technique and we can control powers of the function units using the proposed DVS technique. We simulated the power and circuit simulation for running test program using Spectra with layout extraction data which does not include PAD. We selected the optimum reduced power supply to 0.667 times of the supplied power supply in this paper. The energy efficiency of the proposed 32bit processing unit using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32bit processing unit without using instruction-levels data gating and DVS techniques. The energy efficiency of the proposed instruction-level DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system but a hardware implementation is very easy. The designed high energy efficiency 32bit processing unit can utilize as the coprocessor processing massive data at high speed. © 2008 IEEE.
- KSP 제안 키워드
- DC-DC Converters, Data gating, Dynamic voltage scaling, Gating technique, Hardware Implementation, High Speed, Massive Data, Processing unit, Switching activity, circuit simulation, high energy efficiency