상세정보
학술대회
Low Complexity Soft-decision Demapper for High Order Modulation of DVB-S2 System
- 발행일
- 200811
- 출처
- International SoC Design Conference (ISOCC) 2008, pp.II-37-II-40
- 협약과제
- 08MR2900, 21GHz대역 위성방송 전송기술개발, 장대익
- 초록
- This paper presents an efficient soft-decision demapper interface and a low complexity demapper for highorder modulation scheme. The proposed soft-decision demapper interface can operate at a symbol rate and replace the Parallel to Serial converter by locating between the M-PSK demodulator and the soft-decision demapper. In addition, the proposed softdecision demapper can reduce the hardware complexity by reusing the multipliers. Moreover, the proposed demapper can support high-order modulation modes. The proposed architectures have been thoroughly verified using a FPGA board having the the Xilinx Virtex II. ©2008 IEEE.
- KSP 제안 키워드
- DVB-S2, FPGA Board, Hardware complexity, High order modulation, M-ary phase shift keying(M-PSK), Modulation mode, Modulation scheme, Soft-decision, Xilinx virtex, low-complexity, symbol rate