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Conference Paper
Low Complexity Soft-decision Demapper for High Order Modulation of DVB-S2 System
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- Authors
- Jang Woong Park, Myung Hoon Sunwoo, Pan Soo Kim, Dae-Ig Chang
- Issue Date
- 2008-11
- Citation
- International SoC Design Conference (ISOCC) 2008, pp.II-37-II-40
- Language
- English
- Type
- Conference Paper
- Project Code
- 08MR2900, Development of 21GHz Band Satellite Broadcasting Transmission Technology, Chang Dae Ig
- Abstract
- This paper presents an efficient soft-decision demapper interface and a low complexity demapper for highorder modulation scheme. The proposed soft-decision demapper interface can operate at a symbol rate and replace the Parallel to Serial converter by locating between the M-PSK demodulator and the soft-decision demapper. In addition, the proposed softdecision demapper can reduce the hardware complexity by reusing the multipliers. Moreover, the proposed demapper can support high-order modulation modes. The proposed architectures have been thoroughly verified using a FPGA board having the the Xilinx Virtex II. ©2008 IEEE.
- KSP Keywords
- DVB-S2, FPGA Board, Hardware complexity, High order modulation, M-ary phase shift keying(M-PSK), Modulation mode, Modulation scheme, Soft-decision, Xilinx virtex, low-complexity, symbol rate