상세정보
학술대회
40-Gb/s Two-Parallel Reed-Solomon based Forward Error Correction Architecture for Optical Communications
- 발행일
- 200811
- 출처
- Asia-Pacific Conference on Circuits and Systems (APCCAS) 2008, pp.882-885
- 협약과제
- 08MO1100, 100Gbps급 이더넷 및 광전송기술개발, 김광준
- 초록
- This paper presents a high-speed Forward Error Correction (FEC) architecture based on two- parallel Reed-Solomon (RS) decoder for 40-Gb/s optical communication systems. A high-speed two-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 40-Gb/s RS FEC architecture. The proposed 40-Gb/s RS FEC has been implemented with 0.18-μm CMOS standard cell technology in a supply voltage of 1.8V and Xilinx Virtex4 FPGA. The implementation results show that 16-Ch. RS-based FEC architecture can operate at a clock frequency of 160MHz and has a throughput of 41Gb/s for the Xilinx Virtex4 FPGA. Also RS-based FEC operates at a clock frequency of 400MHz and has a throughput of 102-Gb/s for 0.18-μm CMOS technology. © 2008 IEEE.
- KSP 제안 키워드
- CMOS Technology, Clock frequency, Forward error correction(FEC), High Speed, Reed Solomon(RS), Standard Cell, Supply voltage, Xilinx virtex, optical communication systems