상세정보
학술지
Sub-30 nm Gate Template Fabrication for Nanoimprint Lithography Using Spacer Patterning Technology
- 발행일
- 201102
- 출처
- Journal of Nanoscience and Nanotechnology, v.11 no.2, pp.1625-1628
- ISSN
- 1533-4880
- 출판사
- American Scientific Publishers (ASP)
- 초록
- In this study, we present a spacer patterning technology for sub-30 nm gate template which is used for nano-scale MOSFETs fabrication. A spacer patterning technology using a poly-silicon microfeature and a chemical vapor deposition (CVD) SiO 2 spacer has been developed, and the sub-30 nm structures by conventional dry etching and chemical mechanical polishing are demonstrated. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields a large-area template with critical dimension of minimum-sized features much smaller than that achieved by optical lithography. Copyright © 2011 American Scientific Publishers All rights reserved.
- KSP 제안 키워드
- Chemical Mechanical Polishing(CMP), Chemical Vapor Deposition, Critical dimension, Optical lithography, Poly-silicon, SiO 2, Sub-30 nm structures, Template fabrication, dry etching, film thickness, large area