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Hierarchical Architecture for HEVC Parallel Encoder
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- Authors
- Bumho Kim, Jeong-Woo Lee, Yeon-Jeong Jeong, Ki-Song Yoon
- Issue Date
- 2013-12
- Citation
- Journal of Advanced Information Technology and Convergence, v.3, no.2, pp.41-51
- ISSN
- 2234-1072
- Publisher
- 한국정보기술학회
- Language
- English
- Type
- Journal Article
- Abstract
- The Emerging High Efficiency Video Coding (HEVC) standard offers a significantly better compression rate and higher video quality. HEVC encoders create very high CPU demand, and it is hard for a single core computer to deal with such complex coding computations. To process the high workload of HEVC coding for large-scale video data, the current HEVC draft contains several parallelizing approaches: tile-based parallelization and WPP-level parallelization. In this paper, we adopt additional data parallelism, GOP partitioning, to implement a parallel encoder. We propose the scalable cluster architecture of the HEVC encoder to achieve scalability and a high encoding speed by combining two levels of parallelism, GOP-level parallelism and the HEVC parallel method. The proposed scheme can reduce the large encoding time and significantly improve the coding efficiency. The proposed scalable cluster system is very suitable for high-resolution video such as 4K or 8K containing large amounts of video data.
- KSP Keywords
- Cluster architecture, Cluster system, Coding efficiency, Compression rate, HEVC coding, HEVC encoder, High Efficiency Video coding(HEVC), High Workload, High resolution, Parallel Method, Parallel encoder