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Hierarchical Architecture for HEVC Parallel Encoder
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- 발행일
- 201312
- 출처
- Journal of Advanced Information Technology and Convergence, v.3 no.2, pp.41-51
- ISSN
- 2234-1072
- 출판사
- 한국정보기술학회
- 협약과제
- 13VT1300, 8K급 고해상도 영상 콘텐츠 서비스를 위한 계층구조기반의 고압축, 저손실 콘텐츠 제작/유통/상영 기술개발, 윤기송
- 초록
- The Emerging High Efficiency Video Coding (HEVC) standard offers a significantly better compression rate and higher video quality. HEVC encoders create very high CPU demand, and it is hard for a single core computer to deal with such complex coding computations. To process the high workload of HEVC coding for large-scale video data, the current HEVC draft contains several parallelizing approaches: tile-based parallelization and WPP-level parallelization. In this paper, we adopt additional data parallelism, GOP partitioning, to implement a parallel encoder. We propose the scalable cluster architecture of the HEVC encoder to achieve scalability and a high encoding speed by combining two levels of parallelism, GOP-level parallelism and the HEVC parallel method. The proposed scheme can reduce the large encoding time and significantly improve the coding efficiency. The proposed scalable cluster system is very suitable for high-resolution video such as 4K or 8K containing large amounts of video data.
- KSP 제안 키워드
- Cluster architecture, Cluster system, Coding efficiency, Compression rate, Encoding time, HEVC coding, HEVC encoder, Hierarchical Architecture, High Workload, High-resolution, Parallel Method