상세정보
학술지
A Two-Stage Radix-4 Viterbi Decoder for MB-OFDM UWB Systems
- 발행일
- 200812
- 출처
- ETRI Journal, v.30 no.6, pp.850-852
- ISSN
- 1225-6463
- 출판사
- 한국전자통신연구원 (ETRI)
- 초록
- This letter presents a power efficient 64-state Viterbi decoder (VD) employing a two-stage radix-4 addcompare-select architecture. A class of VD architectures is implemented, and their hardware complexity, maximum operating speed, and power consumption are compared Implementation results show that the proposed VD architecture is suitable for multiband orthogonal frequency-division multiplexing (MB-OFDM) ultra-wideband (UWB) systems, which can support the data rate of 480 Mbps even when implemented using 0.18-μm CMOS technology.
- KSP 제안 키워드
- CMOS Technology, Hardware complexity, MB-OFDM UWB, Operating speed, Orthogonal frequency division Multiplexing(OFDM), Power Consumption, Power-efficient, Radix-4, Two-Stage, UWB system, Ultra-Wide Band(UWB)