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학술지 A Two-Stage Radix-4 Viterbi Decoder for MB-OFDM UWB Systems
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저자
최성우, 강규민, 최상성
발행일
200812
출처
ETRI Journal, v.30 no.6, pp.850-852
ISSN
1225-6463
출판사
한국전자통신연구원 (ETRI)
DOI
https://dx.doi.org/10.4218/etrij.08.0208.0196
협약과제
08MC2200, 초고속 멀티미디어 전송 UWB 솔루션 개발, 최상성
초록
This letter presents a power efficient 64-state Viterbi decoder (VD) employing a two-stage radix-4 addcompare-select architecture. A class of VD architectures is implemented, and their hardware complexity, maximum operating speed, and power consumption are compared Implementation results show that the proposed VD architecture is suitable for multiband orthogonal frequency-division multiplexing (MB-OFDM) ultra-wideband (UWB) systems, which can support the data rate of 480 Mbps even when implemented using 0.18-μm CMOS technology.
KSP 제안 키워드
CMOS Technology, Hardware complexity, MB-OFDM UWB, Operating speed, Orthogonal frequency division Multiplexing(OFDM), Power Consumption, Power-efficient, Radix-4, Two-Stage, UWB system, Ultra-Wide Band(UWB)