상세정보
학술지
Flexible Multi-Core Platform for a Multiple-Format Video Decoder
- 저자
- 조현호, 안용조, 강대범, 지봉일, 심동규, 이재진
- 발행일
- 201508
- 출처
- Journal of Signal Processing Systems, v.80 no.2, pp.163-179
- ISSN
- 1939-8018
- 출판사
- Springer
- 협약과제
- 14MS2100, 다중코어 기반 고성능 SoC의 SW 에뮬레이션 및 Rapid Prototyping 기술개발, 변경진
- 초록
- This paper presents a new multi-core platform that can decode various video compression formats including MPEG-2, MPEG-4, AVS, and H.264/AVC. The developed multi-core platform consists of multiple media cores that are designed based on an application-specific instruction-set processor (ASIP). To improve the decoding speed of each media core, we developed several designated instructions that are useful for decoding various video codecs. In addition, an inter-connected hardware structure and a new synchronization algorithm are proposed to reduce inter-core communication overheads and a shared memory contention on the multi-core platform. We achieved a speed-up of 2.2× in decoding video bitstreams using several designated instructions on the media core. Furthermore, we achieved a speed-up of 5.56× in decoding video bitstreams on the multi-core platform by employing macroblock-row level parallelism, compared with the developed media core without designated instructions. The developed multi-core platform was implemented on a Xilinx Virtex5 LX330 field-programmable gate array (FPGA) that operates at 60혻MHz.
- KSP 제안 키워드
- Application-Specific Instruction-Set Processor, Communication overhead, Field Programmable Gate Arrays(FPGA), Inter-core Communication, MPEG-2, Mpeg-4, Shared Memory, Speed-up, Video Codec, Video compression, Xilinx virtex