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Journal Article
Flexible Multi-Core Platform for a Multiple-Format Video Decoder
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- Authors
- Hyun-Ho Jo, Yong-Jo Ahn, Dae-Beom Kang, Bongil Ji, Dong-Gyu Sim, Jae-Jin Lee
- Issue Date
- 2015-08
- Citation
- Journal of Signal Processing Systems, v.80, no.2, pp.163-179
- ISSN
- 1939-8018
- Publisher
- Springer
- Language
- English
- Type
- Journal Article
- Abstract
- This paper presents a new multi-core platform that can decode various video compression formats including MPEG-2, MPEG-4, AVS, and H.264/AVC. The developed multi-core platform consists of multiple media cores that are designed based on an application-specific instruction-set processor (ASIP). To improve the decoding speed of each media core, we developed several designated instructions that are useful for decoding various video codecs. In addition, an inter-connected hardware structure and a new synchronization algorithm are proposed to reduce inter-core communication overheads and a shared memory contention on the multi-core platform. We achieved a speed-up of 2.2× in decoding video bitstreams using several designated instructions on the media core. Furthermore, we achieved a speed-up of 5.56× in decoding video bitstreams on the multi-core platform by employing macroblock-row level parallelism, compared with the developed media core without designated instructions. The developed multi-core platform was implemented on a Xilinx Virtex5 LX330 field-programmable gate array (FPGA) that operates at 60혻MHz.
- KSP Keywords
- Application-specific instruction set processor, Communication overhead, Field-Programmable Gate Array(FPGA), Inter-core Communication, MPEG-2, Mpeg-4, Shared Memory, Speed-up, Video Compression, Video codec, Video decoder