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학술대회 Partial Conflict-Relieving Programmable Address Shuffler for Parallel Memories in Multi-Core Processor
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저자
권영수, 구본태, 엄낙웅
발행일
200901
출처
Asia and South Pacific Design Automation Conference (ASP-DAC) 2009, pp.329-334
DOI
https://dx.doi.org/10.1109/ASPDAC.2009.4796502
초록
The advancement of process technology enables the integration of multiple cores featuring parallel processing. The requirement of extensive memory bandwidth puts a major performance bottleneck in multi-core architectures for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions required by multiple cores, memory access conflicts caused by simultaneous accesses to an identical memory page by two or more cores limit the performance of multi-core architectures. We propose and evaluate the programmable memory address shuffler associated with the novel memory shuffling algorithm integrated in multi-core architectures with parallel memory system. The address shuffler efficiently translates the requested memory addresses into the shuffled addresses such that access conflicts diminish by analyzing the access pattern of the application. We demonstrate that the shuffling of sub-pages is represented by cyclic linked list which enables partial address shuffling with the minimal number of shuffling table entries. The programmable address shuffler reduces the amount of access conflicts by 83% for pitch-shifting audio decompression. © 2009 IEEE.
KSP 제안 키워드
Access pattern, Linked list, Media applications, Memory Access, Memory System, Memory address, Memory bandwidth, Multi-core architecture, Parallel Processing, Parallel memory, memory page