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Design of 32 bit Parallel Processor Core for High Energy Efficiency using Instruction-Levels Dynamic Voltage Scaling Technique
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- 발행일
- 200903
- 출처
- Journal of Semiconductor Technology and Science, v.9 no.1, pp.1-7
- ISSN
- 1598-1657
- 출판사
- 대한전자공학회 (IEIE)
- 협약과제
- 08MB1800, 유비쿼터스 단말용 부품 모듈, 김종대
- 초록
- Abstract?This paper describes design of high energyefficiency 32 bit parallel processor core using instructtion-levels data gating and dynamic voltage scaling(DVS) techniques. We present instruction-levels datagating technique. We can control activation and switchingactivity of the function units in the proposeddata technique. We present instruction-levels DVS techniquewithout using DC-DC converter and voltagescheduler controlled by the operation system. We cancontrol powers of the function units in the proposedDVS technique. The proposed instruction-levels DVStechnique has the simple architecture than complicatedDVS which is DC-DC converter and voltage schedulercontrolled by the operation system and a hardwareimplementation is very easy. But, the energyefficiency of the proposed instruction-levels DVS techniquehaving dual-power supply is similar to thecomplicated DVS which is DC-DC converter andvoltage scheduler controlled by the operation system.We simulate the circuit simulation for running testprogram using Spectra. We selected reduced powersupply to 0.667 times of the supplied power supply.The energy efficiency of the proposed 32 bit parallelprocessor core using instruction-levels data gatingand DVS techniques can improve about 88.4% thanthat of the 32 bit parallel processor core without usingthose. The designed high energy efficiency 32 bit parallelprocessor core can utilize as the coprocessorprocessing massive data at high speed.
- KSP 제안 키워드
- DC-DC Converters, Data gating, Dynamic voltage scaling, High Speed, Massive Data, Parallel processor, Processor core, circuit simulation, high energy efficiency, operation system, power supply