상세정보
학술대회
Efficient Synchronizer Architecture Using Common Autocorrelator for DVB-S2
- 발행일
- 200905
- 출처
- International Symposium on Circuits and Systems (ISCAS) 2009, pp.1533-1536
- 출판사
- IEEE
- 협약과제
- 09MR3200, 21GHz대역 위성방송 전송기술개발, 장대익
- 초록
- This paper presents an efficient synchronizer architecture using the common autocorrelator for Digital Video Broadcasting via Satellite, Second generation (DVB-S2). To achieve the satisfactory performance under worst channel condition and the efficient H/W resource utilization of functional synchronization blocks which have been implemented, we propose a new efficient common autocorrelator structure. The proposed architecture can ensure the decrease by about 92% multipliers and 81% adders compared with the direct implementation. Moreover, it has been thoroughly verified with an FPGA board and R&S?꽓 SFU broadcast test equipment. ©2009 IEEE.
- KSP 제안 키워드
- DVB-S2, Digital video broadcasting, FPGA Board, Second generation(2G), Test Equipment, channel condition, resource utilization