상세정보
학술대회
A 24-Parallel Processing DS-UWB System
- 발행일
- 200905
- 출처
- International Symposium on Consumer Electronics (ISCE) 2009, pp.554-557
- 출판사
- IEEE
- 협약과제
- 09MR6500, 10GHz 이하 대역에서 Dynamic Spectrum Access를 위한 상호 공존성(Coexistence) 기준 연구, 홍헌진
- 초록
- We present a hardware efficient 24-parallel processing architecture for the binary phase-shift keying (BPSK) direct sequence ultra-wideband (DS-UWB) system. A DS-UWB baseband modem is implemented and tested on the field programmable gate arrays (FPGAs) with a digital-to-analog (D/A) converter operating at the sampling rate of 1.32 GHz. Experimental results show that the DS-UWB prototype system delivers high definition (HD) content over a 5-m UWB channel with less than 1×10-9 bit error rate. ©2009 IEEE.
- KSP 제안 키워드
- Binary Phase Shift Keying, Bit Error Rate(And BER), DS-UWB, Direct-sequence(DS), Field Programmable Gate Arrays(FPGA), Hardware efficient, High definition, Parallel processing architecture, Prototype system, Sampling rate, UWB channel