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Conference Paper A 24-Parallel Processing DS-UWB System
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Authors
Kyu Min Kang, Sang Sung Choi
Issue Date
2009-05
Citation
International Symposium on Consumer Electronics (ISCE) 2009, pp.554-557
Publisher
IEEE
Language
English
Type
Conference Paper
DOI
https://dx.doi.org/10.1109/ISCE.2009.5156870
Project Code
09MR6500, A Study on the radio requirements of coexistence for dynamic spectrum access, Hong Heon Jin
Abstract
We present a hardware efficient 24-parallel processing architecture for the binary phase-shift keying (BPSK) direct sequence ultra-wideband (DS-UWB) system. A DS-UWB baseband modem is implemented and tested on the field programmable gate arrays (FPGAs) with a digital-to-analog (D/A) converter operating at the sampling rate of 1.32 GHz. Experimental results show that the DS-UWB prototype system delivers high definition (HD) content over a 5-m UWB channel with less than 1×10-9 bit error rate. ©2009 IEEE.