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Conference Paper
Compact Design of a Combined MixColumn/InvMixColumn Transformation Module for AES
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- Authors
- Yong Sung Jeon, Jong Wook Han
- Issue Date
- 2009-07
- Citation
- International Conference on Computer Design (CDES) 2009, pp.38-41
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper has presented a compact combined MixColumns/InvMixColumns transformation module for the AES hardware implementation. The presented architecture provides a high level of resource sharing between the MixColumn transformation and the InvMixColumn transformation. The combined Mix-Columns\InvMixColumns transformation module with the proposed optimization method requires an area cost of 182 XOR gates to generate the 32-bit output. Therefore, the number of XOR gates for the proposed module is the smallest of all of the combined MixColumns\InvMixColumns transformation modules reported to date.
- KSP Keywords
- Compact design, Hardware Implementation, area cost, optimization methods, resource sharing