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A 2.85mW 0.12mm2 1.0V 11-bit20-MS/s Algorithmic ADC in 65nm CMOS
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- Authors
- Jae Won Nam, Young Deuk Jeon, Young Kyun Cho, Sang Gug Lee, Jong Kee Kwon
- Issue Date
- 2009-09
- Citation
- European Solid-State Circuits Conference (ESSCIRC) 2009, pp.468-471
- Language
- English
- Type
- Conference Paper
- Project Code
- 09MB2100, Development of Analog Circuit Techniques for Mixed SoC based on 45nm CMOS Technology, Kwon Jong-Kee
- Abstract
- An 11-bit 20-MS/s algorithmic analog-to-digital converter (ADC) based on a dynamic biasing technique is proposed. A dynamic biasing technique is employed to an operational transconductance amplifier (OTA) for power reduction in sub-conversion stages. Besides, a distinct sampling clock scheme is taken to pre-amplifier for reducing aperture time errors. The prototype ADC is fabricated in a 65nm 1P6M CMOS process and features a maximum signal-to-noise-ratio and a spurious-free-dynamic-range of 60.4dB, and 69.2dB at Nyquist input frequency with 20MS/s from a 1.0V supply, respectively. About 22% of OTA power dissipation is reduced without performance degradation and totally 2.85mW is consumed. © 2009 IEEE.
- KSP Keywords
- 65nm CMOS, Analog to digital converter(ADC), Biasing Technique, CMOS Process, Clock scheme, Distinct sampling, Operational transconductance amplifier, Pre-amplifier, Sampling clock, Signal noise ratio(SNR), Signal-to-Noise