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A Triple Gain Mode Digitally Controlled Amplifier in CMOS Process
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- Authors
- Bonghyuk Park, Jaeho Jung
- Issue Date
- 2012-05
- Citation
- Microwave and Optical Technology Letters, v.54, no.5, pp.1263-1266
- ISSN
- 0895-2477
- Publisher
- John Wiley & Sons
- Language
- English
- Type
- Journal Article
- Abstract
- A high dynamic range, wide-band triple gain mode amplifier has been developed using CMOS 0.18-μm technology.The proposed low-noise amplifier (LNA) consists of feedback architecture in the first stage and cascode topology in the second stage. The frequency response of 2.0-3.5 GHz is demonstrated in this work. In high-gain mode, measured results show a noise figure (NF) of 2.6-2.9 dB, gain of 25.4-28.2 dB, and input P1dB of -19.0 dBm with 10.9 mA DC current. In mid-gain mode, the LNA achieves 4.2-6.5 dB NF and 21.3-22.5 dB gain with 11.0 mA current consumption. In low-gain mode, 6.7-8.5 dB NF, 10.2-12.5 dB gain, and -10 dBm input P1dB with 11.0 mA current are realized. © 2012 Wiley Periodicals, Inc.
- KSP Keywords
- 3.5 GHz, CMOS Process, Cascode Topology, Current consumption, DC current, Digitally controlled, First stage, Frequency response, High Gain, High dynamic range, Low-Noise Amplifier(LNA)