상세정보
학술대회
Two-Parallel Concatenated BCH Super-FEC Architecture for 100-GB/S Optical Communications
- 발행일
- 200910
- 출처
- Workshop on Signal Processing Systems (SIPS) 2009, pp.36-39
- 협약과제
- 09MH1200, 100Gbps급 이더넷 및 광전송기술개발, 김광준
- 초록
- This paper presents a high-speed Forward Error Correction (FEC) architecture based on the concatenated BCH code for 100-Gb/s optical communication systems. The concatenated BCH code consists of BCH(3860, 3824) and BCH(2040, 1930), which provides 7.98dB net coding gain at 10-12 corrected bit error rate without additive overhead as compared with the Reed-Solomon(255, 239) standardized in ITU-T G.975 and G.709. This architecture has been implemented with 90-nm CMOS standard cell technology in a supply voltage of 1.1V. The implementation results show that the concatenated BCH Super-FEC architecture can operates at a clock frequency of 400MHz and has a throughput of 102.4-Gb/s for 90-nm CMOS technology. ©2009 IEEE.
- KSP 제안 키워드
- 90-nm, BCH codes, Bit Error Rate(And BER), CMOS Technology, Clock frequency, Forward error correction(FEC), High Speed, ITU-T, Net coding gain, Reed Solomon(RS), Standard Cell