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Impact of Sn/Zn Ratio on the Gate Bias and Temperature-Induced Instability of Zn-In-Sn-O thin Film Transistors
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- Issue Date
- 2009-10
- Citation
- Applied Physics Letters, v.95, no.17, pp.173508-1-173508-3
- ISSN
- 0003-6951
- Publisher
- American Institute of Physics (AIP)
- Language
- English
- Type
- Journal Article
- Abstract
- We investigated the effect of the Sn/Zn ratio in the amorphous Zn-In-Sn-O (ZITO) system on the gate voltage stress-induced stability of the resulting thin film transistors (TFTs). The device stability of the TFTs with a composition channel of Zn:In:Sn=0.35:0.20:0.45 (device C) was dramatically improved, while those of the devices with Zn:In:Sn=0.45:0.20:0.35 and 0.40:0.20:0.40 suffered from deep level trap creation in the channel and charge trapping, respectively. The stability enhancement of device C can be attributed to its having the lowest total trap density, which was corroborated by the superior temperature stability of the subthreshold current region in the temperature range from 298 to 398 K. Therefore, the Sn atoms are believed to act as a stabilizer of the amorphous ZITO network, which is similar to the role of Ga in the In-Ga-Zn-O system. © 2009 American Institute of Physics.
- KSP Keywords
- Charge trapping, Deep level, Device stability, In-Ga-Zn-O(IGZO), Stress-induced, Temperature range, Temperature stability, Thin-Film Transistor(TFT), Voltage stress, Zn-In-Sn-O, gate bias