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Impact of device configuration on the temperature instability of Al–Zn–Sn–O thin film transistors
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- Authors
- Jae Kyeong Jeong, Shin Hyuk Yang, Doo Hee Cho, Sang Hee Ko Park, Chi Sun Hwang, Kyoung Ik Cho
- Issue Date
- 2009-10
- Citation
- Applied Physics Letters, v.95, no.12, pp.123505-1-123505-3
- ISSN
- 0003-6951
- Publisher
- American Institute of Physics (AIP)
- Language
- English
- Type
- Journal Article
- Abstract
- We compared the effect of the temperature on the device stability of Al-Zn-Sn-O (AZTO) thin film transistors (TFTs) with top gate and bottom gate architectures. While the bottom gate device without any passivation layer on the AZTO channel layer showed a large threshold voltage (Vth) shift of 1.6 V after heating it from 298 to 398 K, the naturally passivated top gate device exhibited a smaller Vth shift of 0.6 V. This different behavior is discussed based on the concept of the thermal activation energy of the subthreshold drain current. It is proposed that the suitable passivation and lower interfacial trap density for the top gate TFT are responsible for its superior temperature stability compared to the bottom gate device. © 2009 American Institute of Physics.
- KSP Keywords
- Al-Zn, Bottom gate, Channel layer, Device configuration, Device stability, Drain current, Interfacial trap, Temperature stability, Thermal activation energy, Thin-Film Transistor(TFT), Vth shift